Capabilities

Massive MIMO systems for long-range and high-mobility communications
Millimeter wave systems with integrated access and back-haul
Tera Hz systems for integrated sensing and communication
Front-haul, side-haul and back-haul transport link optimization for energy efficient network deployment
Open RAN technologies to minimize the solution cost, enhance the interoperability, and to avoid the vendor lock-in
Data-driven AI/ML workflows to optimize the RAN performance
Design, implementation and performance optimization of open- and closed-loop massive multiple-input and multiple-output (MIMO) transmission technologies such as spatial multiplexing, space-time-frequency coding, transmit and receive beamforming
Design, implementation and performance optimization of single-user and multi-user link adaptation, modulation and coding scheme adaptation, scheduling, and radio resource management
Link-level simulations to improve the receiver performance margins
System-level simulations for network throughput optimization
Digital pre-distortion and crest factor reduction algorithms to improve the energy efficiency
Handover and random access optimization for low-delay network access

Compiler and mapper toolset for deep learning model optimization
Data path acceleration with optimized TOPS/Watt
Chiplet-based architecture to scale up the inference with a large number of model parameters
Neuromorphic, neural inspired, and analog approaches to energy efficient learning and inference
Optimization of machine learning models for tiny microcontrollers and processors

Architectural exploration
RTL design and coding, hand-optimization of RTL code to improve timing closure and to reduce the logic size
Synthesis, physical design, and functional simulations
Static timing analysis (STA) and design for testability (DFT)
Gate-level simulations, pattern translation and debug
Custom ASIC development using FPGA based specifications
Optimal CAD design flows for ASIC design, including scripting and scan insertion tools
Custom silicon design for hardware acceleration of AI/ML (DNNs/CNNs/RNNs), signal processing (FFTs, matrix computations, beamforming), communication (encoders and decoders), security (encryption and decryption) and front-haul processing (compression and decompression)

Co-design of compute, memory, communication, and authentication for battery-constrained devices
Secure data exfiltration
Location and privacy preserving system operation
Secure virtualization and aggregation of multiple edge devices
System design and optimization for fault tolerance, sensor diversity, redundancy, recovery from failure, and secure remote operations

Spectrum sensing and spectrally efficient operation in contested, congested and denied operation
Advanced waveforms for low-probability of detection (LPD), low-probability of interception (LPI) and jam-resistant operations
Direction finding and emitter localization
Sparsity-exploiting and high-resolution signal processing
Secure compression and exfiltration of RF data
Multi-channel space-time adaptive array processing for clutter suppression and interference mitigation
Multi-functional RF system design and optimization for communications, radar, and RF sensing

High-fidelity physics-based sensor and propagation condition modeling
Pre- and post-processing of high-volume sensor data
Software-centric sensor calibration
Automatic target recognition, image registration, clutter removal, and sensor fusion
Simulation acceleration using GPUs and FPGAs
Real-time and embedded implementation of sensor processing algorithms